Conventional nonvolatile computer memory requires three terminal MOSFET-based devices. The layout of such devices is not ideal, usually requiring an area of at least 8f2 for each memory cell, where f is the minimum feature size. However, not all memory elements require three terminals. If, for example, a memory element is capable of changing its electrical properties (e.g., resistivity) in response to a voltage pulse, only two terminals are required. With only two terminals, a cross point array layout that allows a single cell to be fabricated to a size of 4f2 can be utilized. The performance of cross point arrays utilizing two-terminal memory elements would be further improved if one were able to read and write to multiple elements simultaneously, so as to speed data transfer, especially if such data transfers were accomplished via either page mode or burst mode.
It would therefore be desirable to fabricate a cross point array from two-terminal memory elements. To speed the data transfer process, it would further be desirable to read and write to multiple memory plugs of a cross point array simultaneously, for example by employing page mode and/or burst mode.